1. Field of the Invention
The present invention relates to a control apparatus for electrical devices. More particularly, the present invention relates to a control apparatus for controlling a plurality of electrical devices by transmitting multiple control signals through a small number of electrical lines for controlling, and detecting the state of each of the electrical devices.
2. Description of the Prior Art
In general, the amount of electrical devices equipped in vehicles, ships or various control apparatus has been increasing. The wiring required for complicated electrical devices has become difficult and the finding of faults in order to make necessary repairs has become difficult.
In order to overcome such difficulties, it has been proposed that a control system for controlling a plurality of electrical devices be used by transmitting multiple control signals through a small number of control signal transmission lines (wires).
It is also necessary to prevent breakage or damage to the electrical devices by detecting a fault in the electrical devices and to prevent erroneous operation of the control apparatus due to a "rush current" or a "starting current" at the initiation of the driving of the electrical devices, such as a lamp, motor or the like.
FIG. 1 is a block diagram showing a basic embodiment of a multiple control apparatus for transmitting time division multiple control signals and for controlling n numbers of electrical devices.
In FIG. 1, the control apparatus comprises electrical devices 1a-1n; a central operation device 2; a reference timing signal generation circuit 3; a control signal generation circuit 4; a reference timing signal transmission line 5; a control signal transmission line 6; terminal operation devices 7a-7n corresponding to the electrical devices 1a-1n; signal division circuits 8a-8n; driving circuits 9a-9n; set-reset flips-flops 10a-10n (hereinafter referred to as R-S flip-flops); resistances 11a-11n; transistors 12a-12n for driving the electrical devices 1a-1n; terminals 13a-13n connected to a DC power source (not shown); and contacts 14a-14n for connecting the transistors 12a-12n to the electrical devices 1a-1n.
FIGS. 2a-2e are a timing chart for illustrating the operation of the control apparatus of FIG. 1. FIG. 2a shows the output waveform of the reference timing signal generation circuit 3 including the reference timing signal pulse P. FIG. 2b shows the output waveform a. the control signal pulses Ta-Tn. FIGS. 2c and 2d show the output waveforms of the signal division circuit 8a and FIG. 2e shows the output of the R-S flip-flop 10a
The operation of the control apparatus of FIG. 1 is briefly described referring to the timing charts of FIGS. 2a-2e. The reference timing signal generation circuit 3 generates the reference timing signal pulse P as shown in FIG. 2a and transmits it to the reference timing signal transmission line 5.
The control signal generation circuit 4 generates a control signal depending upon the reference timing signal as shown in FIG. 2b and transmits it to the control signal transmission line 6.
The control signal comprises control signal pulses Ta-Tn corresponding to the electrical devices 1a-1n and a synchronizing signal S which is of a longer pulse width than those of the control signal pulses Ta-Tn. When a control signal pulse Ta-Tn is generated, the corresponding electrical device 1a-1n is driven. On the contrary, when a control signal pulse Ta-Tn is not generated (such as shown by the dotted line), then the corresponding electrical devices 1a-1n is not driven. A terminal operation device 7a-7n controls the corresponding electrical device 1a-1n depending upon the control signal generated by the control signal generation circuit 4.
Since all of the terminal operation devices 7a-7n have the same structure, only terminal operation device 7a is described in detail. The signal division circuit 8a is connected to the reference timing signal transmission line 5 and the control signal transmission line 6, whereby the reference timing signal pulses P are counted to detect the synchronizing signal having a long pulse width, so as to identify the initiation of the repeating period of the multiple control signal. The signal division circuit 8a counts the reference timing signal pulses P to detect the transmission of the control signal pulse Ta during the time period corresponding to the electrical device 1a, and a signal therefrom is applied to the set terminal Sa and the reset terminal Ra of the R-S flip-flop 10a as shown in FIGS. 2c and 2d.
The control signal pulse Ta is transmitted at the time t.sub.1, and the signal pulse U of FIG. 2c is applied at that time to the set terminal Sa of the R-S flip-flop 10a whereby the output signal of the output terminal Qa is changed as shown in FIG. 2e, and the transistor 12a is turned on to drive the electrical device 1a.
At the time t.sub.1, the signal pulse V as shown in FIG. 2d, is not generated at the reset terminal Ra of the R-S flip-flop 10a.
At the time t.sub.2, the control signal pulse Ta is not transmitted; the signal pulse U is not applied to the set terminal Sa of the R-S flip-flop 10a; the signal pulse V is applied to the reset terminal Ra; the output signal of the output terminal Qa is changed as shown in FIG. 2e; the transistor 12a is turned off and the driving of the electrical device 1a is stopped.
It should be understood that the other terminal operation devices 7b-7n act similar to the operation just described and that the electrical devices 1b-1n are driven when the corresponding control signal pulses Tb-Tn are transmitted.
On the other hand, the electrical devices 1b-1n are not driven when the control signal pulses Tb-Tn are not transmitted.
In the terminal operation devices 7a-7n of the control apparatus of FIG. 1, when one of the electrical devices 1a-1n causes a short circuit fault in the ON state of the transistors 12a-12n, an overcurrent will be passed through the transistor 12a-12n and thereby break or damage the same. Accordingly, it is necessary to prevent such a short-circuit fault.
FIG. 3 shows a circuit for protecting a short-circuit fault in the ON state of the transistors 12a-12n of the control device of FIG. 1 and thereby preventing breaking or damaging of the same. In FIG. 3, only the terminal operating circuit 7a is exemplified however, it is to be understood that the other terminal operation circuits 7b-7n can have a similar structure.
The circuit of FIG. 3 comprises a state detecting circuit 15a which includes a NOR circuit 16a and a state signal generation circuit 17a which includes an R-S flip-flop 18a and an OR circuit 19a.
FIGS. 4a-4g show timing charts for illustrating the operation of the circuit of FIG. 3. In FIGS. 4a-4e, like reference numerals designate identical or corresponding parts to FIGS. 2a-2e; FIG. 4f shows the output of the NOR circuit 16a and FIG. 4g shows the output of the R-S flip-flop 18a.
When the control signal plate Ta is transmitted to the electrical device 1a, the output signal of the R-S flip-flop 10a at the time t.sub.1 in FIG. 4e becomes of a low level and the electrical device 1a is driven. When a short-circuit fault is caused at the time t.sub.2, the potential at the contacts 14a of the electrical device 1a and the transistor 12a is at a low level potential, even though the transistor 12a is turned on, whereby the NOR circuit 16a detects the short-circuit fault to generate a high level output signal as shown in FIG. 4f. This high level signal is then applied to the set terminal Sa' of the R-S flip-flop 18a. The high level signal at the output terminal Qa' of the R-S flip-flop 18a then becomes of a high level, whereby the R-S flip-flop 10a is reset; and the driving of the electrical device 1a is stopped. The width of the output signal pulse W of the NOR circuit 16a which is shown in FIG. 4f, is decided by the delay time of the circuit operation.
Once a short-circuit fault is detected, the R-S flip-flop 18a will continue to reset the R-S flip-flop 10a until such time as the driving stop command is transmitted to the electrical device 1a.
When the control signal pulse Ta is not transmitted at the time t.sub.3 and the state of the contact 14a is released to the normal state, then the R-S flip-flop 18a is reset, and the signal at the output terminal Qa' has no relationship with the normal operation.
In accordance with the above, a short-circuit fault is detected to prevent breakage or damage of the transistor 12a.
In the circuit of FIG. 3, when the electrical device 1a is a device such as a lamp or a motor, a high "rush current" or a high "starting current" is passed at the initiation of the driving.
Accordingly, a long time is required for the potential at the contact 14a to reach the power voltage at the initiation of driving.
In the transient state, the output signal of the R-S flip-flop 10a is of a low level so as to drive the electrical device 1a. However, since the potential of the contact 14a is of a low level, the NOR circuit 16a generates an output signal to set the R-S flip-flop 18a.
Thus, with the above described terminal operation device of FIG. 3, a problem exists in that the transient state can be detected as a short-circuit fault, and the R-S flip-flop 10a is immediately reset whereby the electrical device 1a is not driven.